Intel’s 15 Most Unforgettable x86 CPUs-Part 1

8086: The First PC processor

The 8086 was the first x86 processor—Intel had already released the 4004, the 8008, the 8080 and the 8085. This 16-bit processor could manage 1 MB of memory using an external 20-bit address bus. The clock frequency chosen by IBM (4.77 MHz) was fairly low, though the processor was running at 10 MHz by the end of its career.

The first PCs used a derivative of this processor, the 8088, which had only an 8-bit (external) data bus. An interesting aside is that the control systems in the US space shuttles use 8086 processors and NASA was forced to buy some from eBay in 2002 since Intel could no longer supply them.

Intel 8086

Code name	N/A
Date released	1979
Architecture	16 bits
Data bus	16 bits
Address bus	20 bits
Maximum memory	1 MB
L1 cache	no
L2 cache	no
Clock frequency	4.77-10 MHz
FSB	same as clock frequency
FPU	8087
SIMD	no
Fabrication process	3,000 nm
Number of transistors	29,000
Power consumption	N/A
Voltage	5 V
Die surface area	16 mm²
Connector	40-pin

80286: 16 MB Of Memory, But Still 16 Bits

Released in 1982, the 80286 was 3.6 times faster than the 8086 at the same frequency. It could manage up to 16 MB of memory, but the 286 was still a 16-bit processor. It was the first x86 equipped with a memory management unit (MMU), allowing it to manage virtual memory. Like the 8086, it did not have a floating-point unit (FPU), but could use a x87 co-processor chip (80287). Intel offered these processors at a maximum frequency of 12.5 MHz, whereas their competitors reached 25 MHz.

Intel 80286

Code name	N/A
Date released	1982
Architecture	16 bits
Data bus	16 bits
Address bus	24 bits
Maximum memory	16 MB
L1 cache	No
L2 cache	No
Clock frequency	6–12 MHz
FSB	same as clock frequency
FPU	80287
SIMD	No
Fabrication process	1,500 nm
Number of transistors	134,000
Power consumption	N/A
Voltage	5 V
Die surface area	49 mm²
Connector	68-pin

386: 32-Bit and Cache Memory

Intel’s 80836 was the first x86 with a 32-bit architecture. Several versions of this processor were offered. The two best known are the 386 SX (Single-word eXternal), which had a 16-bit data bus, and the 386 DX (Double-word eXternal) with a 32-bit data bus. Two other versions are worth noting, though: the SL, which was the first x86 to offer management of a cache (external) and the 386EX, used in the space program (the Hubble telescope uses this processor).

Intel 80386 DX

Code name	P3
Date released	1985
Architecture	32 bits
Data bus	32 bits
Address bus	32 bits
Maximum memory	4096 MB
L1 cache	0 KB (controller sometimes present)
L2 cache	no
Clock frequency	16-33 MHz
FSB	same as clock frequency
FPU	80387
SIMD	no
Fabrication process	1,500-1,000 nm
Number of transistors	275,000
Power consumption	2 W @ 33 MHz
Voltage	5 V
Die surface area	42 mm² @ 1µ
Connector	132 pins

The 486: An FPU And Multipliers Too

The 486 is emblematic of a certain generation who were first discovering computers. In fact, the very famous 486 DX2/66 was long considered the minimum configuration for gamers. This processor, released in 1989, ushered in several interesting new features, like an on-chip FPU, data cache, and the first clock multiplier. The former consisted of an x87 coprocessor built into the 486 DX (not SX) series. An 8 KB Level 1 cache was built into the processor (write-through type, then write-back with slightly better performance). There was also the possibility of a Level 2 cache on the motherboard (at the bus frequency).

The second generation of 486s had a CPU multiplier, since the processor operated faster than the FSB, with DX2 (2x multiplier) and DX4 (3x multiplier) versions. Another anecdote: the “487SX” sold as an FPU for the 486SX was actually a full 486DX that disabled and took the place of the first processor.

Intel 80486 DX

Code name	P4, P24, P24C
Date released	1989
Architecture	32 bits
Data bus	32 bits
Address bus	32 bits
Maximum memory	4096 MB
L1 cache	8 KB
L2 cache	Motherboard (FSB frequency)
Clock frequency	16-100 MHz
FSB	16-50 MHz
FPU	On chip
SIMD	No
Fabrication process	1,000–800 nm
Number of transistors	1,185,000
Power consumption	N/A
Voltage	5 V–3.3 V
Die surface area	81 – 67 mm²
Connector	168 pins

The DX4 had a 16 KB cache and a few more transistors: 1.6 million. This processor, using a 600 nm process and measuring 76 mm², consumed less power than the original 486 (at a voltage of 3.3 V).

Intel Pentium: A Bothersome Bug

The Pentium, introduced in 1993, was interesting for more than one reason. It was the first x86 to drop the traditional model number for a more attractive name, since Intel wasn’t allowed to trademark a name made up of numbers only. It’s also famous because of a bug it contained. On the first generations of Pentiums, certain division operations produced an incorrect result. Intel replaced the processors, but the damage was done. A very rare error gave rise to the first big IT media buzz.

The Pentium was sold in three different versions, the first without a CPU multiplier, the second with a multiplier (including the very familiar Pentium 166), and the last with the SIMD instruction set for x86s, MMX. The Pentium MMX also increased the size of the Level 1 cache and brought in a few minor improvements. This was the first Intel x86 capable of executing two instructions in parallel. The L2 cache was on the motherboard with these processors (running at the frequency of the FSB).

Intel Pentium (MMX)

Code name	P5, P54	P55 (Pentium MMX)
Date released	1993	1997
Architecture	32 bits	32 bits
Data bus	64 bits	64 bits
Address bus	32 bits	32 bits
Maximum memory	4096 MB	4096 MB
L1 cache	8 KB + 8 KB	16 KB + 16 KB
L2 cache	Motherboard (FSB frequency)	Motherboard (FSB frequency)
Clock frequency	60-200 MHz	133-300 MHz
FSB	50-66 MHz	60-66 MHz
FPU	on chip	on chip
SIMD	no	MMX
Fabrication process	800-600-350 nm	350 nm
Number of transistors	3.1-3.3 million	4.5 million
Power consumption	8-16 W	4-17 W
Voltage	5 V-3.3 V	2.8 V
Die surface area	294-163-90 mm²	141 mm²
Connector	Socket 4, 5 or 7	Socket 7

Here’s a little explanation of the Pentium bug: certain calculations using the FPU resulted in erroneous results. This was fairly rare—though sources disagree about exactly how rare—and Intel replaced the defective processors free of charge. Here’s an example of a Pentium error:

4195835.0/3145727.0 = 1.333 820 449 136 241 002 (correct result) 4195835.0/3145727.0 = 1.333 739 068 902 037 589 (incorrect result on a defective Pentium)

Pentium Pro: The First To Handle Over 4 GB Of Memory

The Pentium Pro, released in 1995, was the first x86 CPU able to manage more than 4 GB of RAM using Physical Address Extension (PAE), 36-bit address size, and thus 64 GB. An interesting point is that this processor was also the first P6 (the architecture the Core 2 processors are loosely derived from) and also the first x86 to include a Level 2 cache on the processor instead of on the motherboard. In fact, between 256 KB and 1 MB of cache were placed next to the CPU, on the same socket, making the L2 cache on-package as opposed to on-chip, clocked at the same frequency as the CPU.

This processor also had a bit of a performance issue. It ran great in 32-bit applications, but was much slower with software still written in 16 bits (like Windows 95). The cause was simple: access to 16-bit registers caused problems with management of the (32-bit) registers, which canceled out the advantages of the Pentium Pro’s out-of-order architecture.

Intel Pentium Pro

Code name	P6
Date released	1995
Architecture	32 bits
Data bus	64 bits
Address bus	36 bits
Maximum memory	64 GB
L1 cache	8 KB + 8 KB
L2 cache	external, 256-1024 KB (CPU frequency)
Clock frequency	150-200 MHz
FSB	60-66 MHz
FPU	built-in
SIMD	N/A
Fabrication process	600-350 nm
Number of transistors	5,500,000 + cache
Power consumption	29-47 W
Voltage	3.3 V
Die surface area	306-196 mm² + cache
Connector	Socket 8

The cache measured 202 mm² (256 KB at 500 nm), 242 mm² (512 KB at 350 nm), or 484 mm² (1 MB at 350 nm). The number of transistors in the cache was 15.5 million (256 KB), 31 million (512 KB), or 62 million (1 MB).

Pentium II and III: Brothers

Released in 1997, the Pentium II was an adaptation of the Pentium Pro aimed at the general public. It was quite similar to the Pentium Pro, but the cache memory was different. Instead of using a cache at the same frequency as the processor (which is expensive), the 512 KB Level 2 cache operated at half-frequency. In addition, the Pentium II abandoned the classic socket for a cartridge containing the processor and the Level 2 cache, which was in the cartridge and not on the motherboard or in the processor itself.

New features compared to the Pentium Pro were essentially MMX (SIMD) support and a doubling of the Level 1 cache. The first Pentium III (Katmai) was very similar to the Pentium II. Released in 1999, its new feature was essentially support for SSE (SIMD instructions), but the rest was identical.

Intel Pentium II and III

Code name	Klamath (Pentium II 0.35µ), Deschutes (Pentium II 0.25µ), Katmai (Pentium III)
Date released	1997, 1998, 1999
Architecture	32 bits
Data bus	64 bits
Address bus	36 bits (32 bits on the P III)
Maximum memory	64 GB (4 GB on the P III)
L1 cache	16 KB + 16 KB
L2 cache	external, 512 KB (1/2 CPU frequency)
Clock frequency	233-300 MHz (Klamath), 300-450 MHz (Deschutes), 450-600 MHz (Klamath)
FSB	66-100-133 MHz
FPU	built-in
SIMD	MMX (SSE)
Fabrication process	350 nm (Klamath), 250 nm (Deschutes, Katmai)
Number of transistors	7,500,000 + cache (Pentium II), 9,500,000 + cache (Pentium III)
Power consumption	25-35 W
Voltage	2.8 V (0.35µ), 2 V (0.25µ)
Die surface area	204 mm² (0.35µ), 131 mm² (0.25µ), 128 mm² (PIII) + cache
Connector	Slot 1

The Pentium II and III had 512 KB of Level 2 cache (31 million transistors). One Pentium II actually had an on-chip 256 KB Level 2 cache—the Pentium II Mobile Dixon. Using a 180 nm fabrication process, this processor was significantly faster than the desktop versions

Celeron and Xeon: Intel Aims At The High/Low End

At the end of the 1990s, Intel launched two of its best-known processor brands: Celeron and Xeon. The former was aimed at the budget market and the latter at servers, and sometimes workstations. The first Celeron (Covington) was a Pentium II without a Level 2 cache, and suffered extremely poor performance, whereas the Pentium II Xeon had a large cache. Even now, both brands still exist—Celeron for the entry-level market (generally with a reduced cache and a slower FSB) and Xeon for servers (with a fast FSB, sometimes more cache, and high clock speeds).

Intel quickly added a cache to the Celeron with the Mendocino model (128 KB). The Celeron 300A is famous for its overclocking capacities, able to go 50% or more above its rated clock speed much of the time.

Intel Celeron and Intel Xeon

Code name	Covington, Mendocino	Drake
Date released	1998	1998
Architecture	32 bits	32 bits
Data bus	64 bits	64 bits
Address bus	32 bits	36 bits
Maximum memory	4 GB	64 GB
L1 cache	16 KB + 16 KB	16 KB + 16 KB
L2 cache	0 KB/128 KB (internal, CPU frequency)	external, 512 KB-2,408 KB (CPU frequency)
Clock frequency	266-300 MHz/300-533 MHz	400-450 MHz
FSB	66 MHz	100 MHz
FPU	built in	built in
SIMD	MMX	MMX
Fabrication process	250 nm	250 nm
Number of transistors	7,500,000/19,000,000	7,500,000 + cache
Power consumption	16–28 W	30-46 W
Voltage	2 V	2 V
Die surface area	131 mm²/154 mm²	131 mm² + cache
Connector	Slot1/Socket 370 PPGA	Slot 2

Like the Pentium II, Xeon had an external L2 cache inside the processor cartridge. Its capacity was between 512 KB and 2 MB, and the number of transistors between 31 million and 124 million.

The Pentium III Hits 1 GHz

The Pentium III Coppermine was the first commercial x86 processor from Intel to attain a clock speed of 1 GHz; a 1.13 GHz version was even released, but was quickly taken off the market because it was unstable. This new version of the Pentium III improved the Level 2 cache—now on-die. It was faster than the 512 KB external cache on the first model and was touted as a feature able to speed up the Internet experience. It was released in three versions: server (Xeon), entry-level (Celeron), and mobile (with the first version of SpeedStep).

Intel Pentium III

Code name	Coppermine
Date released	1999
Architecture	32 bits
Data bus	64 bits
Address bus	32 bits
Maximum memory	4 GB
L1 cache	16 KB + 16 KB
L2 cache	internal, 256 KB (CPU frequency)
Clock frequency	500–1,133 MHz
FSB	100-133 MHz
FPU	built in
SIMD	MMX (SSE)
Fabrication process	180 nm
Number of transistors	28.1 million
Power consumption	25-35 W
Voltage	1.6 V, 1.8 V
Die surface area	106 mm²
Connector	Slot 1-Socket 370 FCPGA

A slightly improved version (Tualatin), with more L2 cache (512 KB) and centering on a 130 nm process, was released in 2002. Essentially intended for servers (PIII-S) and mobile devices, it was less common in consumer-level machines.

The Pentium 4: A Lot Of Noise Over Very Little

In November 2000, Intel announced its new processor, the Pentium 4. With a higher clock speed (at least 1,400 MHz), this processor had a major drawback in that its performance wasn’t as good as competing models on a per-clock basis. AMD’s Athlon (and even the Pentium III) performed better at the same frequency. Complicating matters, Intel tried to shift to Rambus’ RDRAM memory (the only memory at the time capable of meeting the requirements of the CPU’s FSB), but failed. Expensive and hot, the Pentium 4 nonetheless managed, with many modifications, to more or less stay in the competition for a few years (by adding L3 cache and technologies like Hyper-Threading).

Intel Pentium 4 32-bit

Code name	Willamette	Northwood	Prescott
Date released	2000	2001	2004
Architecture	32 bits	32 bits	32 bits
Data bus	64 bits	64 bits	64 bits
Address bus	32 bits	32 bits	32 bits
Maximum memory	4 GB	4 GB	4 GB
L1 cache	8 KB + 12 Kµops	8 KB + 12 Kµops	16 KB + 12 Kµops
L2 cache	256 KB	512 KB	1,024 KB
Clock frequency	1.3-2 GHz	1.8–3.4 GHz	2.4–3.8 GHz
FSB	400 MHz	400, 533, 800 MHz	533, 800 MHz
SIMD	MMX, SSE, SSE2	MMX, SSE, SSE2	MMX, SSE, SSE2, SSE3
SMT/SMP	no	Hyper-Threading (certain versions)	Hyper-Threading
Fabrication process	180 nm	130 nm	90 nm
Number of transistors	42 million	55 million	125 million
Power consumption	66-100 W	54-137 W	94-151 W
Voltage	1.7 V	1.55 V	1.25–1.5 V
Die surface area	217 mm²	146 mm²	112 mm²
Connector	Socket 423/Socket 478	Socket 478	Socket 478/LGA775

Mobile versions (with a variable multiplier), Celeron versions (with a smaller L2 cache), and Xeon versions (with an L3 cache) of the Pentium 4 were sold. Hyper-Threading and the L3 cache are two technologies that first appeared on servers and were then adapted to standard processors (though L3 cache was available only on the expensive EE models).

We should also mention the FSB, which was clocked at a fourth of the nominal clock frequency, using what is called Quad Data Rate (QDR) technology—a 400 MHz bus is actually 100 MHz QDR, 533 MHz is 133 MHz QDR, etc. Finally, 64-bit versions of the Pentium 4 appeared in 2005, which we’ll talk about later on.

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